1. Field of the Invention
This invention relates to a delta sigma modulator, specifically to a delta sigma modulator provided with an integrator equipped with a switching circuit and a D/A converter that converts an output of the integrator into an analog output, in which the output of the D/A converter is fed back to the integrator. This invention also relates to a delta sigma A/D converter provided with a digital filter in addition to the delta sigma modulator.
2. Description of the Related Art
FIG. 7 is a block diagram showing a conventional delta sigma modulator (ΔΣ modulator). In the delta sigma modulator, a first integrator 2 integrates a sum of an input signal and an output of a one-bit D/A converter 1, a second integrator 3 further integrates a sum of an output of the first integrator 2 and the output of the one-bit D/A converter 1, and a quantizer 4 quantizes an output of the second integrator 3 to generate a one-bit digital signal. The one-bit digital signal outputted from the quantizer 4 is converted by the one-bit D/A converter 1 into an analog signal that is the output of the one-bit D/A converter fed back and inputted to the first integrator 2 and the second integrator 3.
Each of the first integrator 2 and the second integrator 3 is provided with a switching circuit composed of a plurality of switches and a plurality of capacitors and an operational amplifier having an input terminal and an output terminal connected with each other through a capacitor. Charge/discharge cycles of the capacitors are controlled by controlling turning on/off of the plurality of switches. A clock generation circuit 5 provides a plurality of clocks to control the turning on/off of the plurality of switches.
The delta sigma modulator outputs a clock signal with a duty ratio that varies corresponding to a level of the input signal, as shown in FIG. 8. For example, the duty ratio of the output clock signal is 50% when the level of the input signal is equal to a center voltage of a dynamic range of the input signal, the duty ratio becomes larger than 50% when the level of the input signal gets closer to an upper limit of the dynamic range, and the duty ratio becomes less than 50% when the level of the input signal gets closer to a lower limit of the dynamic range. The delta sigma A/D converter is obtained by adding a digital filter 6 that reduces quantization noise in the output of the delta sigma modulator caused by the quantizer 4.
The plurality of clocks differs from each other in rising timing and falling timing. In other words, they differ from each other in phase. The clock generation circuit 5 is made of a circuit as shown in FIG. 9 in order to generate the clocks as described above. That is, the clocks to control the switches are generated by level-shifting an externally inputted clock with a level shifter 51 and delaying the level-shifted clock by a delay circuit 52 that is made of a plurality of inverters connected in series. The delay time of the plurality of clocks is adjusted by the number of inverters. A clock CKD is delayed relative to a clock CK in an example shown in FIG. 9.
Further descriptions on the delta sigma modulator are provided in Japanese Patent Application Publication Nos. 2002-100992 and H09-205369, for example.
However, since the delay time of the clocks is adjusted by the number of the inverters in the clock generation circuit 5 in the conventional delta sigma modulator, it is difficult to increase the delay time of the clocks significantly (because the number of the inverters increases significantly).
In addition, when a frequency of the input clock is varied to modify an operational frequency of the delta sigma modulator, the number of inverters in the delay circuit 52 has to be adjusted in order to maintain correlations among the phases of the clocks as required.